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Senior Verification Engineer Location: Rotterdam, Netherlands Salary: Competitive Salary + Benefits A leading provider in the semiconductor and security space is seeking a talented Senior Verification Engineer to join its Security team. This is an opportunity to work alongside some of the brightest engineers and innovators to develop cutting-edge products that ensure faster and safer data management. As a Senior Verification Engineer you will report to the Senior Manager of Verification Engineering. You will participate in the verification of secure ASIC cores in collaboration with cross-functional teams, including ASIC design engineers, architects, verification engineers, security experts, and cryptographers. While prior experience in cryptography and hardware security is not mandatory, a willingness to learn is essential. The company embraces a hybrid work environment, encouraging employees to spend at least three days per week onsite and up to two days working remotely. Key Responsibilities • Design and implement verification test plans, testbenches, infrastructure, and platforms to ensure robust products. • Support all phases of hardware projects, including bring-up, testing, debugging, and coverage analysis. • Collaborate with release teams to address customer integration and related requirements. Experience: • Minimum of four years in verification engineering or a related field. • Proven expertise in verifying complex and configurable digital designs. Skills: • Proficiency in standard ASIC verification techniques, including test planning, testbench creation, and functional coverage. • Experience with SystemVerilog-based constrained random stimulus generation, scoreboards, assertions, and self-checking methodologies. • Familiarity with verification methodologies like UVM or OVM. • Competence in Unix-based development environments and scripting (Perl/Python). • Exposure to regression and coverage management tools. This role offers a competitive compensation package, including salary, bonus, equity, and employee benefits. For further information and a confidential discussion please contact Meg Evans at IC Resources.

Senior Verification Engineer - RISC-V Start-Up Are you passionate about microprocessor architecture and ready to make an impact as a Senior Verification Engineer? Interested in a company that’s pushing the boundaries of high-performance RISC-V cores? As a Senior Verification Engineer, you’ll be a key player in the Verification Team, ensuring the accuracy and functionality of complex digital designs using cutting-edge methodologies and tools.This is your opportunity to work on groundbreaking projects that shape the future of AI, machine learning, and semiconductor technology as a Senior Verification Engineer. Required Experience: Proven experience in seeing through projects including multiple successful tape-outs • Experience working in a UVM-based verification environment • Proficiency in SystemVerilog • Strong skills in scripting languages (Python, Perl, Bash, TCL) • Knowledge of revision control systems (git, svn) • Experience with both formal verification is a plus • Fluent English (speaking and writing skills) Knowledge in one or more of the following areas is essential: • Coherent systems and CHI protocol • Cache structures and parameters • PCle and high-speed communications protocols Ready to shape the future of technology? If you’re excited about the world of microprocessor architecture and want to be part of a dynamic team where your work truly matters, please contact Meg Evans at IC Resources for more information.

Senior Digital Verification Engineer - Trento We are currently looking for a talented and experienced Senior Digital Verification Engineer to join an innovative and dynamic Digital Design team. As a Senior Digital Verification Engineer, you will play a key role in leading the verification of digital designs for complex systems, working on cutting-edge projects in the semiconductor industry. You will be instrumental in developing and refining verification methodologies, as well as driving best practices in verification processes across multiple sites. Working for a global brand, with beautiful offices set in the foothills of the mountain ranges in Trento, northern Italy. You will be part of a cutting edge R&D team focused on the design, development and verification of CMOS image sensors. Responsibilities: • Lead Digital Design Verification projects, managing work allocation for contributors and reporting progress to senior management. • Develop and refine advanced verification methodologies to improve efficiency across sites, ensuring the highest standards of quality. • Analyse design specifications to create comprehensive verification plans for complex digital blocks and system components. • Maintain and manage a digital regression environment, ensuring high functional and code coverage. • Debug tests autonomously, collaborating effectively with designers to resolve issues. • Write, integrate, and debug analogue models to support AMS verification teams. • Contribute to the development of verification methodologies for imaging systems and system model integration (e.g., SystemC). • Apply Continuous Integration (CI) principles, working with tools like Jenkins to optimise workflows. • Collaborate with teams across Europe and Japan to align verification strategies and share knowledge on best practices. Key Requirements: • A strong technical background in electronics, semiconductor technology, or physics, with a PhD/MSc in Engineering, Physics, or a related field, or equivalent professional experience. • Significant experience in the digital verification domain, preferably with expertise in CMOS Image Sensors. • Advanced knowledge of UVM (Universal Verification Methodology) and digital verification processes. • Proficiency in scripting languages such as Python, Perl, Tcl/shell, or Makefile. • Strong communication and coordination skills, with the ability to work effectively with both internal teams and external contractors. • Proven experience working with cross-functional, multi-national, and remote teams. • Fluency in English, both written and spoken. For more information on this opportunity please contact Jordan Browne.

Are you looking for the next step in your career in UVM Verification? Would you like to learn from skilled experts in a friendly and growing environment with exciting projects? If the answer is yes, then this may be the perfect opportunity for you! I have a key requirement for an experienced/senior Verification Engineer - to work for an established company based in the Grenoble area - who focus on design and verification services for a number of major clients. As the senior verification engineer, you will be responsible for R&D projects and the development of verification environments (SystemVerilog / UVM /…), VIP components and giving training to other engineers. Technical skills • 3-5+ years' IP or SoC verification experience • Confident knowledge with SystemVerilog and UVM methodology • SoC architecture • Bus communication protocols knowledge - AMBA / AXI etc. • OOP (Object Oriented Programming) and scripting skills / hardware & software - perl / shel / python / c • Fluent English - and preferably French • Master's Degree - this is a bonus If you would like to know more, please contact Rob Click here to contact this recruiter Resources for a discussion.

Senior Verification Engineer Based in the East Midlands, our successful and expanding Semiconductor client is seeking a Senior Verification Engineer. With a growing global reputation in High-Speed Communications, my client is expanding in the UK and are looking for a Senior Verification Engineer to play a vital role in the business, utilising the latest techniques, tools and technologies for design verification activities. Key requirements • 5+ years’ experience in the semiconductor industry. • Expert in digital design verification, using standardised methodologies, i.e. UVM • Experience in constrained random testbench development. • Proven track record in verifying complex designs (preferably in high volume ASIC applications) • Familiarity with high level protocols (e.g. PCIe, USB, DP) is an added bonus • Familiarity with SerDes is highly desirable • Experience with SystemVerilog Assertions (SVA) and formal verification is valuable On offer is a very competitive basic salary and bonus scheme, plus relocation and visa sponsorship if needed. For more information please contact Rachel Mason at IC Resources.

Working for a cutting edge company, focusing on a complex processor for quantum computing technology. This is a brilliant opportunity for a senior verification engineer to join them. As Principal / Lead Verification Engineer, you will be tasked with leading ASIC / FPGA verification duties, and developing the UVM environment. Must-have experience: • Circa 10 years' experience in digital or AMS verification • VHDL / SystemVerilog • RTL design / coding • ASIC / FPGA digital verification knowledge • Tcl / Python or similar coding / scripting • UVM (Nice-to-have experience): • Previous experience setting up or developing a UVM environment. • embedded software • DevOps / software automation / CI/CD • Other verification packages (e.g. OVM, OSVVM, Cocotb) • Formal verification *Visa sponsorship is available