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I am seeking a Principal Verification Engineer to join a leading Chip and Silicon IP provider. The Principal Verification Engineer will get the chance to join some of the brightest inventors and engineers in the world to develop products that make data faster and safer. You will join a global company that makes industry-leading memory interface chips and Silicon IP to advance data centre connectivity and solve the bottleneck between memory and processing. Responsibilities • Create digital verification plans and work closely with system and design engineers. • Implement digital test-benches in SystemVerilog and UVM to apply constrained random stimulus and checks. • Implement Systemverilog Assertions (SVA). • Track bugs, functional coverage, and RTL code coverage. • Work with design and systems teams to close bugs as they arise. • Mentor junior designers. For this role, at Principal level, you are required to have at least 7 years’ experience in Verification (with a PhD) or circa 10 with a BsC or MsC. Other qualifications include: • Significant experience with coding in System Verilog or Verilog and UVM methodology. • Experience in Verification of DDR memory interfaces is highly desirable. • Significant experience with standard ASIC Verification flow/software tools. • Experience working in Analog/Mixed-signal products is highly desirable. • Experience in leading and driving technical solutions across organisation. Being a top company, you can expect a competitive compensation package including base salary, bonus, equity, employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership. For more information and a confidential discussion please contact Rachel Mason at IC Resources.

Working for a cutting edge company, focusing on a complex processor for quantum computing technology. This is a brilliant opportunity for a senior verification engineer to join them. As Principal / Lead Verification Engineer, you will be tasked with leading ASIC / FPGA verification duties, and developing the UVM environment. Must-have experience: • Circa 10 years' experience in digital or AMS verification • VHDL / SystemVerilog • RTL design / coding • ASIC / FPGA digital verification knowledge • Tcl / Python or similar coding / scripting • UVM (Nice-to-have experience): • Previous experience setting up or developing a UVM environment. • embedded software • DevOps / software automation / CI/CD • Other verification packages (e.g. OVM, OSVVM, Cocotb) • Formal verification *Visa sponsorship is available

Principal Verification Engineer Edinburgh, UK The company is seeking a talented Principal Verification Engineer to join its dynamic team. The successful candidate will be responsible for leading and participating in the verification of complex hardware designs. This role requires a deep understanding of verification methodologies and strong expertise in UVM. Responsibilities • Architects and defines verification strategy for complex hardware designs • Designs, develops, and enhances the verification environment using UVM methodology • Drives metric-driven verification processes to ensure high-quality and reliable designs • Mentors and provides technical guidance to junior verification engineers • Collaborates with cross-functional teams to ensure successful verification and validation of designs • Contributes to the continuous improvement of the verification process and methodologies Qualifications • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field • Extensive experience in verification of complex hardware designs • Proficiency in UVM and other advanced verification methodologies • Strong understanding of verification architecture and metric-driven verification • Excellent problem-solving and debugging skills • Strong communication and collaboration skills • Leadership experience is a plus Day-to-day • Develops and maintains robust, reusable verification components • Leads and participates in verification planning and strategy meetings • Collaborates with design and architecture teams to understand design specifications • Analyses and debugs failures in the verification environment • Mentors and guides junior verification engineers on best practices and methodologies • Stays updated with the latest industry trends and advancements in verification methodologies