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ASIC Verification Engineer The company is seeking an experienced ASIC Verification Engineer to join their dynamic team. The ideal candidate will have a passion for cutting-edge technology, a strong understanding of CPU and RISC-V processors, and expertise in verification methodologies including UVM and formal verification tools such as Jaspergold. Responsibilities • Collaborates with design and verification teams to develop and execute verification plans for complex ASIC designs • Utilises UVM methodology to create and maintain verification environments • Develops and executes test benches and test cases to ensure comprehensive verification coverage • Utilises formal verification techniques to enhance verification efficiency and completeness • Works with cross-functional teams to resolve design and verification issues Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field; Master's degree preferred • Proven experience in ASIC verification with a focus on CPU and RISC-V processors • Strong understanding of UVM methodology and hands-on experience with formal verification tools such as Jaspergold • Solid understanding of verification techniques and methodologies • Excellent problem-solving and debugging skills • Ability to work effectively in a fast-paced, collaborative team environment • Successful candidates must have the right to work in the UK Day-to-day • Collaborates with design and verification teams to develop and execute verification plans • Creates and maintains verification environments using UVM methodology • Develops and executes test benches and test cases • Utilises formal verification techniques to enhance verification efficiency • Participates in cross-functional team meetings to resolve design and verification issues Location This position is located in Cambridge. Remote work options may be available.

Working for a cutting edge company, focusing on a complex processor for quantum computing technology. This is a brilliant opportunity for a senior verification engineer to join them. As Principal / Lead Verification Engineer, you will be tasked with leading ASIC / FPGA verification duties, and developing the UVM environment. Must-have experience: • Circa 10 years' experience in digital or AMS verification • VHDL / SystemVerilog • RTL design / coding • ASIC / FPGA digital verification knowledge • Tcl / Python or similar coding / scripting • UVM (Nice-to-have experience): • Previous experience setting up or developing a UVM environment. • embedded software • DevOps / software automation / CI/CD • Other verification packages (e.g. OVM, OSVVM, Cocotb) • Formal verification *Visa sponsorship is available