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Senior DFT Engineer Location: Switzerland (Lausanne), Germany (Dortmund), or UK (Northampton or Reading) Are you an experienced DFT Engineer eager to drive innovation in the semiconductor industry? We have an exciting opportunity for a Senior DFT Engineer to join a high-tech, fast-growing company making strides in high-speed, energy-efficient chip-chip link solutions. If you’re passionate about pushing your limits and thrive in a challenging, forward-thinking environment, this could be the role for you. Role overview: As a Senior DFT Engineer, you will collaborate with multi-site teams to drive the design, implementation, and simulation of complex DFT architectures, managing projects from initial stages through to successful tape-outs. This role involves developing and leading DFT methodologies and tool flows for intricate, multi-million gate designs, including those with Analog/high bandwidth SerDes. You will define comprehensive test plans, contribute to functional and structural test development, and support the definition of HTOL test suites, cycle times, and burn-in PCB board bring-up. Key Skills: • Experience in DFT, including architecture specification, implementation, test pattern development, and verification. • Proven expertise in MBIST insertion, simulation, and verification on RTL and Gate Level Netlist. • Solid experience with Scan insertion, Scan compression, Stuck-At, At-Speed testing, and coverage analysis. • Proficiency in Scan ATPG pattern generation, simulation, and debug on RTL and Gate Level Netlist. • Hands-on experience with state-of-the-art EDA tools for DFT, design, and verification (Mentor, Cadence, Synopsys). • Familiarity with STA DFT test mode timing constraint development and analysis. • Strong Verilog HDL knowledge, with experience in simulators and waveform debugging tools. • Proficiency in TCL scripting; Python scripting skills are advantageous. This role offers the opportunity to be part of a dynamic team at the forefront of technological advancement in the semiconductor sector. As a Senior DFT Engineer, you’ll play a crucial role in driving innovation and shaping solutions for the future of electronics. If you’re looking for a position that challenges you and allows you to impact cutting-edge technology, we’d love to hear from you. Please contact Lucy Edmondson at IC Resources for more information.

Job Title: Senior DFT Engineer Location: UK (Oxford or Bristol) Contract Type: Full-time, permanent position (Hybrid Working) Salary: £75,000- £100,000 (Depending on experience) Summary: My client is looking for an experienced Senior Design for Test (DFT) Engineer with specialist expertise in digital ASIC/SoC development. The successful candidate will have a strong academic background and extensive knowledge of DFT in complex ASIC/SoC designs, including power management, memories, and Analog IP elements. This is an SME organisation with a high volume of projects available across a long list of industry sectors, including Medical, Automotive & Telecommunications. Responsibilities: • Take full ownership of DFT, BIST, and test-pattern generation for complex digital and mixed-signal ASIC designs. • Offer consultancy on test-related issues to clients during pre-sales and implementation phases. • Configure, run, and maintain EDA tool flows related to DFT, BIST, and test pattern generation. • Collaborate with front-end and back-end teams to implement and verify DFT throughout the development process. • Ensure customer fault-coverage expectations and requirements are met. • Act as the primary contact between the company and any sub-contracted back-end service providers. • Create test specification documentation for sub-contractors providing test services. • Keep abreast of the latest ASIC Test methodologies and best practices to maintain up-to-date expertise and services. Key Skills / Experience: Essential: • A 1st or 2.1 degree in Electronics, Physics, or a related field from a Tier 1 university. • 5-10 years of industry experience with a proven track record in DFT across multiple successful ASIC projects. • Strong skills in DFT implementation, including: • Architectural specification • Tool-based and manual implementation • IP integration, including CPUs, Analog Macros, and IO PHYs • BIST and memory repair integration • Coverage analysis and improvement • ATPG, manual, and semi-automatic TPG, including simulation-based methods • At-speed test methodologies • DFT for power-managed designs • Generation of STA and scenario/mode constraints • Proficiency with a complete EDA vendor DFT tool suite (e.g., Siemens Tessent suite). • Knowledge of STA tools (e.g., Synopsys Primetime, Cadence Tempus) is a plus. • Experience with the complete SoC design flow and associated tools and methodologies. • Experience with RTL and gate-level simulations and related debugging for DFT verification. • VHDL/Verilog coding skills. • Experience working with test service providers, including test hardware and program specification, bring-up, and debug. Personality: • Excellent communication and interpersonal skills. • Strong presentation skills, capable of interacting with senior management. • Self-motivated with a strong customer service orientation and a 'can-do' attitude. • Creative problem-solving abilities. • Team player. • Ability to thrive in a dynamic environment. What is on offer? • Starting salary of up to £100,000 • Flexible hybrid working (Fully remote possibility) • Individual/company performance Bonus scheme 15% of your basic • Company Share scheme • Matched pension contribution of 5% And much more! If this role is of interest, please apply with your most up to date CV. To find out more about Computer Futures please visit XX XX XX XX XX Computer Futures, a trading division of SThree Partnership LLP is acting as an Employment Business in relation to this vacancy | Registered office | 8 Bishopsgate, London, EC2N 4BQ, United Kingdom | Partnership Number | OC387148 England and Wales

Job Title: Senior DFT Engineer Location: UK (Oxford or Bristol) Contract Type: Full-time, permanent position (Hybrid Working) Salary: £50,000- £75,000 Summary: My client is looking for an experienced Senior Design for Test (DFT) Engineer with specialist expertise in digital ASIC/SoC development. The successful candidate will have a strong academic background and extensive knowledge of DFT in complex ASIC/SoC designs, including power management, memories, and Analog IP elements. This is an SME organisation with a high volume of projects available across a long list of industry sectors, including Medical, Automotive & Telecommunications. Responsibilities: • Take full ownership of DFT, BIST, and test-pattern generation for complex digital and mixed-signal ASIC designs. • Offer consultancy on test-related issues to clients during pre-sales and implementation phases. • Configure, run, and maintain EDA tool flows related to DFT, BIST, and test pattern generation. • Collaborate with front-end and back-end teams to implement and verify DFT throughout the development process. • Ensure customer fault-coverage expectations and requirements are met. • Act as the primary contact between the company and any sub-contracted back-end service providers. • Create test specification documentation for sub-contractors providing test services. • Keep abreast of the latest ASIC Test methodologies and best practices to maintain up-to-date expertise and services. Key Skills / Experience: Essential: • A 1st or 2.1 degree in Electronics, Physics, or a related field from a Tier 1 university. • 5-10 years of industry experience with a proven track record in DFT across multiple successful ASIC projects. • Strong skills in DFT implementation, including: • Architectural specification • Tool-based and manual implementation • IP integration, including CPUs, Analog Macros, and IO PHYs • BIST and memory repair integration • Coverage analysis and improvement • ATPG, manual, and semi-automatic TPG, including simulation-based methods • At-speed test methodologies • DFT for power-managed designs • Generation of STA and scenario/mode constraints • Proficiency with a complete EDA vendor DFT tool suite (e.g., Siemens Tessent suite). • Knowledge of STA tools (e.g., Synopsys Primetime, Cadence Tempus) is a plus. • Experience with the complete SoC design flow and associated tools and methodologies. • Experience with RTL and gate-level simulations and related debugging for DFT verification. • VHDL/Verilog coding skills. • Experience working with test service providers, including test hardware and program specification, bring-up, and debug. Personality: • Excellent communication and interpersonal skills. • Strong presentation skills, capable of interacting with senior management. • Self-motivated with a strong customer service orientation and a 'can-do' attitude. • Creative problem-solving abilities. • Team player. • Ability to thrive in a dynamic environment. Position Specifics: • Flexible role with some UK and international travel required. • Applicants must have the right to live and work in the UK. To find out more about Computer Futures please visit XX XX XX XX XX Computer Futures, a trading division of SThree Partnership LLP is acting as an Employment Business in relation to this vacancy | Registered office | 8 Bishopsgate, London, EC2N 4BQ, United Kingdom | Partnership Number | OC387148 England and Wales

Job Title: Senior DFT Engineer Location: UK (Oxford or Bristol) Contract Type: Full-time, permanent position (Hybrid working) Salary: £50,000- £75,000 Summary: My client is looking for an experienced Senior Design for Test (DFT) Engineer with specialist expertise in digital ASIC/SoC development. The successful candidate will have a strong academic background and extensive knowledge of DFT in complex ASIC/SoC designs, including power management, memories, and Analog IP elements. This is an SME organisation with a high volume of projects available across a long list of industry sectors, including Medical, Automotive & Telecommunications. Responsibilities: • Take full ownership of DFT, BIST, and test-pattern generation for complex digital and mixed-signal ASIC designs. • Offer consultancy on test-related issues to clients during pre-sales and implementation phases. • Configure, run, and maintain EDA tool flows related to DFT, BIST, and test pattern generation. • Collaborate with front-end and back-end teams to implement and verify DFT throughout the development process. • Ensure customer fault-coverage expectations and requirements are met. • Act as the primary contact between the company and any sub-contracted back-end service providers. • Create test specification documentation for sub-contractors providing test services. • Keep abreast of the latest ASIC Test methodologies and best practices to maintain up-to-date expertise and services. Key Skills / Experience: Essential: • A 1st or 2.1 degree in Electronics, Physics, or a related field from a Tier 1 university. • 5-10 years of industry experience with a proven track record in DFT across multiple successful ASIC projects. • Strong skills in DFT implementation, including: • Architectural specification • Tool-based and manual implementation • IP integration, including CPUs, Analog Macros, and IO PHYs • BIST and memory repair integration • Coverage analysis and improvement • ATPG, manual, and semi-automatic TPG, including simulation-based methods • At-speed test methodologies • DFT for power-managed designs • Generation of STA and scenario/mode constraints • Proficiency with a complete EDA vendor DFT tool suite (e.g., Siemens Tessent suite). • Knowledge of STA tools (e.g., Synopsys Primetime, Cadence Tempus) is a plus. • Experience with the complete SoC design flow and associated tools and methodologies. • Experience with RTL and gate-level simulations and related debugging for DFT verification. • VHDL/Verilog coding skills. • Experience working with test service providers, including test hardware and program specification, bring-up, and debug. Personality: • Excellent communication and interpersonal skills. • Strong presentation skills, capable of interacting with senior management. • Self-motivated with a strong customer service orientation and a 'can-do' attitude. • Creative problem-solving abilities. • Team player. • Ability to thrive in a dynamic environment. Position Specifics: • Flexible role with some UK and international travel required. • Applicants must have the right to live and work in the UK. To find out more about Computer Futures please visit XX XX XX XX XX Computer Futures, a trading division of SThree Partnership LLP is acting as an Employment Business in relation to this vacancy | Registered office | 8 Bishopsgate, London, EC2N 4BQ, United Kingdom | Partnership Number | OC387148 England and Wales