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Working for a fascinating semiconductor company, who is focussed in RISC-V core IP development; within this team your responsibility will include, but not limited, to: • Deliver RTL to the SoC team, support verification and silicon validation teams, and work with SW teams to support successful deployments of the system. • Evaluate new IPs, driving new IP deployments as well as defining system wide guidelines for IPs requirement in the SoC. • Closely drive resolution of issues and bugs gating the completion of schedule. Skills • 5+ years of solid experience in IP/SoC design. • Good understanding of ASIC design / verification / implementation flows. • Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification. • Hands-on experience with SoC Design, Verilog RTL coding and simulation software. • General knowledge of synthesis, DFT, verification, formal verification, silicon debug. • Working Knowledge with SystemVerilog or Verilog, C or C++, scripting languages such as Python • MUST HAVE - excellent communication skills (ideally in English / Spanish / Catalan) Visa sponsorship and relocation support is available for highly skilled, and relevant qualified engineers

Working for a cutting edge start-up, I am looking to recruit a high-level SOC architect for fascinating and brand-new project work. Based in Netherlands' front-edge start-up community, you will be tasked with the definition and development of a brand new SOC architecture. Key skills / requirements: • BSc / MSc / PhD in Micro-electornics, physics, or similar filed • 10+ years' experience in high-level design and system / SOC architecure • Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, eFuse). • Extensive experience with the Digital ASIC Flow, RTL design, and Debug methodologies (e.g., DFT, JTAG, Scan, BIST). • Extensive knowledge of SOC architecture, set-up / bring-up and all it's associated processes. • SOC design, system design, architecture and IP integration • DSP / signal processing • Digital-AMS chip development Please contact Rob Hudson for more details

Exciting opportunity to work on the latest cutting edge technology in the semiconductor industry. In this new role as senior digital design engineer you will have the opportunity to contribute to advanced technology nodes, consisting of RISC-V designs, CPU architecture, PCIe protocols and machine learning. I am looking to speak with senior digital design engineers - who have experience of, or an interest in: • Degree in Electronics / Microelectronics or similar field • 5+ years' experience in ASIC / FPGA design projects • UVM environments & processes • System Verilog for IP / SOC design of digital ICs / ASIC IP or chips • Complex ASIC/FPGA designs & architecture for advanced technology nodes • RISC-V / CPU / GPU knowledge (is a bonus, but not required) • PCIe knowledge (also a bonus skill) • scripting / coding skills - C/C++, python etc. ***Visa sponsorship and relocation support can be offered if required (dependent on experience/qualifications)***

Digital Design Manager - ASIC IP A fantastic opportunity for a Digital IC Design Manager to join one of industry’s most exciting Semiconductor scale-ups, based in a selection of European locations: Lausanne - Switzerland Reading - UK Dortmund - Germany This world-leading company is pioneering the world’s fastest connectivity chip technology. They currently seek a Digital IC Design Manager to lead a team of 15 front-end RTL Design Engineers, split across several sites. Reporting to the Design Director, the Digital IC Design Manager will lead the development effort, working closely with the analog IC teams, as well as verification and physical design teams to deliver high quality designs that meet performance, power and area requirements. The Digital IC Design Manager will also from time to time be involved in technical hands-on work when required. The role will be around 30% technical hands-on work, 70% managerial responsibilities. The Digital IC Design Manager will have: • Extensive experience within Digital ASIC / SoC Design, with a solid profile in RTL Design • Expertise using appropriate EDA tools • A background within high-speed, low power designs • Exposure to analog / mixed-signal designs would also be beneficial • Strong technical leadership ability On offer is a competitive basic salary, plus company shares options. Get in touch for details! For more information, please contact Rob Hudson at IC Resources

Digital Design Manager - ASIC IP A fantastic opportunity for a Digital IC Design Manager to join one of industry’s most exciting Semiconductor scale-ups, based in a selection of European locations: Lausanne - Switzerland Reading - UK Dortmund - Germany This world-leading company is pioneering the world’s fastest connectivity chip technology. They currently seek a Digital IC Design Manager to lead a team of 15 front-end RTL Design Engineers, split across several sites. Reporting to the Design Director, the Digital IC Design Manager will lead the development effort, working closely with the analog IC teams, as well as verification and physical design teams to deliver high quality designs that meet performance, power and area requirements. The Digital IC Design Manager will also from time to time be involved in technical hands-on work when required. The role will be around 30% technical hands-on work, 70% managerial responsibilities. The Digital IC Design Manager will have: • Extensive experience within Digital ASIC / SoC Design, with a solid profile in RTL Design • Expertise using appropriate EDA tools • A background within high-speed, low power designs • Exposure to analog / mixed-signal designs would also be beneficial • Strong technical leadership ability On offer is a competitive basic salary, plus company shares options. Get in touch for details! For more information, please contact Rob Hudson at IC Resources

Job Title: Senior DFT Engineer Location: UK (Oxford or Bristol) Contract Type: Full-time, permanent position (Hybrid Working) Salary: £75,000- £100,000 (Depending on experience) Summary: My client is looking for an experienced Senior Design for Test (DFT) Engineer with specialist expertise in digital ASIC/SoC development. The successful candidate will have a strong academic background and extensive knowledge of DFT in complex ASIC/SoC designs, including power management, memories, and Analog IP elements. This is an SME organisation with a high volume of projects available across a long list of industry sectors, including Medical, Automotive & Telecommunications. Responsibilities: • Take full ownership of DFT, BIST, and test-pattern generation for complex digital and mixed-signal ASIC designs. • Offer consultancy on test-related issues to clients during pre-sales and implementation phases. • Configure, run, and maintain EDA tool flows related to DFT, BIST, and test pattern generation. • Collaborate with front-end and back-end teams to implement and verify DFT throughout the development process. • Ensure customer fault-coverage expectations and requirements are met. • Act as the primary contact between the company and any sub-contracted back-end service providers. • Create test specification documentation for sub-contractors providing test services. • Keep abreast of the latest ASIC Test methodologies and best practices to maintain up-to-date expertise and services. Key Skills / Experience: Essential: • A 1st or 2.1 degree in Electronics, Physics, or a related field from a Tier 1 university. • 5-10 years of industry experience with a proven track record in DFT across multiple successful ASIC projects. • Strong skills in DFT implementation, including: • Architectural specification • Tool-based and manual implementation • IP integration, including CPUs, Analog Macros, and IO PHYs • BIST and memory repair integration • Coverage analysis and improvement • ATPG, manual, and semi-automatic TPG, including simulation-based methods • At-speed test methodologies • DFT for power-managed designs • Generation of STA and scenario/mode constraints • Proficiency with a complete EDA vendor DFT tool suite (e.g., Siemens Tessent suite). • Knowledge of STA tools (e.g., Synopsys Primetime, Cadence Tempus) is a plus. • Experience with the complete SoC design flow and associated tools and methodologies. • Experience with RTL and gate-level simulations and related debugging for DFT verification. • VHDL/Verilog coding skills. • Experience working with test service providers, including test hardware and program specification, bring-up, and debug. Personality: • Excellent communication and interpersonal skills. • Strong presentation skills, capable of interacting with senior management. • Self-motivated with a strong customer service orientation and a 'can-do' attitude. • Creative problem-solving abilities. • Team player. • Ability to thrive in a dynamic environment. What is on offer? • Starting salary of up to £100,000 • Flexible hybrid working (Fully remote possibility) • Individual/company performance Bonus scheme 15% of your basic • Company Share scheme • Matched pension contribution of 5% And much more! If this role is of interest, please apply with your most up to date CV. To find out more about Computer Futures please visit XX XX XX XX XX Computer Futures, a trading division of SThree Partnership LLP is acting as an Employment Business in relation to this vacancy | Registered office | 8 Bishopsgate, London, EC2N 4BQ, United Kingdom | Partnership Number | OC387148 England and Wales

Working for a leader in the semiconductor industry, I am looking to recruit a high-level System Architect for fascinating and brand-new project work. Based in the beautiful heart of Switzerland's French-speaking region, you will be tasked with the definition, integration and development of complex system architecture of IP & SOC products with a range of applications. All the while surrounded by a diverse and international workforce, and stunning scenery that provides an exceptional quality of life. Key skills / requirements (the client will consider a combination or elements of the following criteria) • BSc / MSc / PhD in Micro-electornics, physics, or similar filed • 10+ years' experience in complex SOCs • Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, eFuse), or flash / DDR / HBM / cache coherency • CPU / GPU processor architecture • Extensive experience with the Digital ASIC Flow, RTL design, and Debug methodologies (e.g., DFT, JTAG, Scan, BIST). • Extensive knowledge of SOC architecture, set-up / silicon bring-up, validation and all it's associated processes. • SOC design, system design, architecture and IP selection & integration • platform architecture / concept design • DSP / signal processing / communication and interconnect protocols • Digital-AMS chip development - digital to analog interfaces • Reusable IP, IP-Xact • low-power, performance and optimisation • low level software, firmware and embedded requirements - drivers, controllers etc. Applicants must have EU working rights. NO visa sponsorship is available.

Job Title: Senior DFT Engineer Location: UK (Oxford or Bristol) Contract Type: Full-time, permanent position (Hybrid working) Salary: £50,000- £75,000 Summary: My client is looking for an experienced Senior Design for Test (DFT) Engineer with specialist expertise in digital ASIC/SoC development. The successful candidate will have a strong academic background and extensive knowledge of DFT in complex ASIC/SoC designs, including power management, memories, and Analog IP elements. This is an SME organisation with a high volume of projects available across a long list of industry sectors, including Medical, Automotive & Telecommunications. Responsibilities: • Take full ownership of DFT, BIST, and test-pattern generation for complex digital and mixed-signal ASIC designs. • Offer consultancy on test-related issues to clients during pre-sales and implementation phases. • Configure, run, and maintain EDA tool flows related to DFT, BIST, and test pattern generation. • Collaborate with front-end and back-end teams to implement and verify DFT throughout the development process. • Ensure customer fault-coverage expectations and requirements are met. • Act as the primary contact between the company and any sub-contracted back-end service providers. • Create test specification documentation for sub-contractors providing test services. • Keep abreast of the latest ASIC Test methodologies and best practices to maintain up-to-date expertise and services. Key Skills / Experience: Essential: • A 1st or 2.1 degree in Electronics, Physics, or a related field from a Tier 1 university. • 5-10 years of industry experience with a proven track record in DFT across multiple successful ASIC projects. • Strong skills in DFT implementation, including: • Architectural specification • Tool-based and manual implementation • IP integration, including CPUs, Analog Macros, and IO PHYs • BIST and memory repair integration • Coverage analysis and improvement • ATPG, manual, and semi-automatic TPG, including simulation-based methods • At-speed test methodologies • DFT for power-managed designs • Generation of STA and scenario/mode constraints • Proficiency with a complete EDA vendor DFT tool suite (e.g., Siemens Tessent suite). • Knowledge of STA tools (e.g., Synopsys Primetime, Cadence Tempus) is a plus. • Experience with the complete SoC design flow and associated tools and methodologies. • Experience with RTL and gate-level simulations and related debugging for DFT verification. • VHDL/Verilog coding skills. • Experience working with test service providers, including test hardware and program specification, bring-up, and debug. Personality: • Excellent communication and interpersonal skills. • Strong presentation skills, capable of interacting with senior management. • Self-motivated with a strong customer service orientation and a 'can-do' attitude. • Creative problem-solving abilities. • Team player. • Ability to thrive in a dynamic environment. Position Specifics: • Flexible role with some UK and international travel required. • Applicants must have the right to live and work in the UK. To find out more about Computer Futures please visit XX XX XX XX XX Computer Futures, a trading division of SThree Partnership LLP is acting as an Employment Business in relation to this vacancy | Registered office | 8 Bishopsgate, London, EC2N 4BQ, United Kingdom | Partnership Number | OC387148 England and Wales

Verification Engineer – Senior and Principal levels Bristol, UK This is a fantastic opportunity to help support the build of a new Bristol based Chip Team, working on innovative, class leading silicon. My client has opened a small design centre in the bustling City of Bristol. They are developing a novel photonic-electronic architecture that will bring fully homomorphic encryption to the world. The development provides a huge opportunity to become the ubiquitous choice for this new upcoming market across multiple industry sectors. In order to achieve their goal of bringing this technology to the mass market, they are assembling a highly skilled team to build a complex SoC. With the successful recruitment of several Design and Verification Engineers into the team, they continue to build on this and are hiring for 2/3 more Verification Engineers. In this role, you would support the Verification group in defining the verification and validation strategy for the SoC. Working with the SoC Architect and Design team, you would help define and execute the strategy to build a SoC that achieves their technical and commercial goals. To be successful for this role you must have a strong background in SoC verification. UVM experience is a must. You will have: • A proven track record in SoC verification with exposure to all phases in the flow – requirements collection, methodology and test plans, testbench implementation, coverage closure, documentation etc. • Deep understanding of modern verification and validation techniques including formal, UVM/OVM/eRM, low power, emulation • Good knowledge of the SoC design flow from specification to silicon tape-out For more information and a chat about this superb opportunity, please contact Rachel Mason at IC Resources

Job Title: Senior DFT Engineer Location: UK (Oxford or Bristol) Contract Type: Full-time, permanent position (Hybrid Working) Salary: £50,000- £75,000 Summary: My client is looking for an experienced Senior Design for Test (DFT) Engineer with specialist expertise in digital ASIC/SoC development. The successful candidate will have a strong academic background and extensive knowledge of DFT in complex ASIC/SoC designs, including power management, memories, and Analog IP elements. This is an SME organisation with a high volume of projects available across a long list of industry sectors, including Medical, Automotive & Telecommunications. Responsibilities: • Take full ownership of DFT, BIST, and test-pattern generation for complex digital and mixed-signal ASIC designs. • Offer consultancy on test-related issues to clients during pre-sales and implementation phases. • Configure, run, and maintain EDA tool flows related to DFT, BIST, and test pattern generation. • Collaborate with front-end and back-end teams to implement and verify DFT throughout the development process. • Ensure customer fault-coverage expectations and requirements are met. • Act as the primary contact between the company and any sub-contracted back-end service providers. • Create test specification documentation for sub-contractors providing test services. • Keep abreast of the latest ASIC Test methodologies and best practices to maintain up-to-date expertise and services. Key Skills / Experience: Essential: • A 1st or 2.1 degree in Electronics, Physics, or a related field from a Tier 1 university. • 5-10 years of industry experience with a proven track record in DFT across multiple successful ASIC projects. • Strong skills in DFT implementation, including: • Architectural specification • Tool-based and manual implementation • IP integration, including CPUs, Analog Macros, and IO PHYs • BIST and memory repair integration • Coverage analysis and improvement • ATPG, manual, and semi-automatic TPG, including simulation-based methods • At-speed test methodologies • DFT for power-managed designs • Generation of STA and scenario/mode constraints • Proficiency with a complete EDA vendor DFT tool suite (e.g., Siemens Tessent suite). • Knowledge of STA tools (e.g., Synopsys Primetime, Cadence Tempus) is a plus. • Experience with the complete SoC design flow and associated tools and methodologies. • Experience with RTL and gate-level simulations and related debugging for DFT verification. • VHDL/Verilog coding skills. • Experience working with test service providers, including test hardware and program specification, bring-up, and debug. Personality: • Excellent communication and interpersonal skills. • Strong presentation skills, capable of interacting with senior management. • Self-motivated with a strong customer service orientation and a 'can-do' attitude. • Creative problem-solving abilities. • Team player. • Ability to thrive in a dynamic environment. Position Specifics: • Flexible role with some UK and international travel required. • Applicants must have the right to live and work in the UK. To find out more about Computer Futures please visit XX XX XX XX XX Computer Futures, a trading division of SThree Partnership LLP is acting as an Employment Business in relation to this vacancy | Registered office | 8 Bishopsgate, London, EC2N 4BQ, United Kingdom | Partnership Number | OC387148 England and Wales

Design Verification Engineer - AI Accelerator Chips Interested in pushing the boundaries of AI technology as a Design Verification Engineer? Join a leading team in developing next-generation, high-performance, AI accelerator chips that drive innovations across industries like automotive, HPC, security, and more. This opportunity offers a unique chance for a Design Verification Engineer to be at the forefront of AI hardware innovation, where your work will directly impact the development of cutting-edge technologies used across multiple industries. Here’s why you should be excited about joining this team as a Design Verification Engineer. What You'll Do: • Work on cutting-edge AI-specific semiconductor systems focused on low power consumption and high performance. • Play a key role in verifying ASIC design, architecture, and micro-architecture using advanced methodologies like UVM, Formal Verification, and Emulation. • Collaborate with cross-functional teams, including software developers, hardware engineers, and post-silicon teams, to deliver first-pass silicon success. Why This Opportunity? Work on Groundbreaking AI Technology You'll contribute to the design and verification of next-generation AI accelerator chips that power machine learning and deep learning applications. This is a chance to work on products that push the limits of performance and efficiency, making a real difference in industries like automotive, high-performance computing, and more. Cutting-Edge Tools and Methodologies You'll leverage the latest verification methodologies, including UVM, Formal Verification, and Emulation. This role gives you hands-on experience with state-of-the-art tools and technologies, enhancing your skillset and keeping you ahead of the curve in your career. Pioneering the Future of AI If you’re passionate about AI, this is your chance to be a part of something transformative. You’ll be working on chips that will drive the next wave of AI innovation, making systems smarter, faster, and more efficient. What I’m Looking For: • Strong experience in architecting and implementing Design Verification environments and completing the full verification cycle. • Proficiency in UVM methodologies, with a focus on AI/ML applications. • Hands-on experience with EDA tools, Python, and Perl scripting for verification environments. • Expertise in SoC design flow, from specification to synthesis, including power and timing analysis. • Experience with high-frequency design considerations, multiple clock domains, and more. • How to Apply: If you're ready to take on an exciting challenge as a Design Verification Engineer, I’d love to hear from you, even if your CV isn’t up to date, please get in touch to discuss this role or other opportunities we have available!